Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
IEEE Transactions on Computers
The warp computer: Architecture, implementation, and performance
IEEE Transactions on Computers
Synthesizing Linear Array Algorithms from Nested FOR Loop Algorithms
IEEE Transactions on Computers
The parallel execution of DO loops
Communications of the ACM
Computer Architecture and Parallel Processing
Computer Architecture and Parallel Processing
Introduction to VLSI Systems
Systolic (VLSI) arrays for relational database operations
SIGMOD '80 Proceedings of the 1980 ACM SIGMOD international conference on Management of data
The Generation of a Class of Multipliers: Synthesizing Highly Parallel Algorithms in VLSI
IEEE Transactions on Computers
Use of VLSI in algebraic computation: Some suggestions
SYMSAC '81 Proceedings of the fourth ACM symposium on Symbolic and algebraic computation
Automatic synthesis of systolic arrays from uniform recurrent equations
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Synthesizing Linear Array Algorithms from Nested FOR Loop Algorithms
IEEE Transactions on Computers
Building and Using a Highly Parallel Programmable Logic Array
Computer - Special issue on experimental research in computer architecture
Mapping Nested Loop Algorithms into Multidimensional Systolic Arrays
IEEE Transactions on Parallel and Distributed Systems
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It has been observed by many researchers that systolic arrays are very suitable for certain high-speed computations. In this paper, using a formal methodology, a single simple programmable linear systolic array capable of solving large number of problems drawn from a variety of applications is designed. The methodology is applicable to problems solvable by sequential algorithms that can be specified as nested for loops of arbitrary depth. The algorithms of this form that can be computed on the array presented in this paper include 25 algorithms dealing with signal and image processing, algebraic computations, matrix arithmetic, pattern matching, database operations, sorting, and transitive closure. Assuming bounded I/O, for 18 of those algorithms the time and storage complexities are optimal, and therefore no improvement can be expected by utilizing dedicated special purpose linear systolic arrays designed for individual algorithms.