Architecture of a FPGA-based coprocessor: the PAR-1

Authors:
J. M. Carrera;E. J. Martinez;S. A. Fernandez;J. M. M. Chaus
Affiliations:
-;-;-;-
Venue:
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Year:
1995

Citing 8
Cited 0

Building and Using a Highly Parallel Programmable Logic Array

Computer - Special issue on experimental research in computer architecture
Field-programmable gate arrays

Field-programmable gate arrays
An array architecture for reconfigurable datapaths

Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs
VHDL programming on splash 2

Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs
Signed digit arithmetic on FPGAs

Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs
Processor reconfiguration through instruction-set metamorphosis

Computer
AnyBoard: An FPGA-Based, Reconfigurable System

IEEE Design & Test
The VLSI Complexity of Sorting

IEEE Transactions on Computers

Quantified Score

Hi-index	0.00

Visualization

Abstract

Abstract: The implementation of a FPGA based coprocessor and its programming methodology are shown. The effects of different sequencing models, and regular and irregular circuits on the hardware and in the programming methodology are discussed. Two examples are described: a sorting network and the kernel of a speech recognition algorithm. The results are still preliminary but they suggest some architectural improvements for general FPGA based computing machines.