Building and Using a Highly Parallel Programmable Logic Array
Computer - Special issue on experimental research in computer architecture
The Art of Computer Programming Volumes 1-3 Boxed Set
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Processor Arrays: Architecture and Applications
Processor Arrays: Architecture and Applications
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
A dynamic instruction set computer
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Continuous and high coverage self-testing of dynamically re-configurable systems
Parallel Computing - Parallel computing in image and video processing
Fast Template Placement for Reconfigurable Computing Systems
IEEE Design & Test
Run-time support for dynamically reconfigurable computing systems
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
A Run-Time Reconfigurable Datapath Architecture for Image Processing Applications
Proceedings of the conference on Design, automation and test in Europe - Volume 3
An optimal algorithm for minimizing run-time reconfiguration delay
ACM Transactions on Embedded Computing Systems (TECS)
Optimal reconfiguration sequence management
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
PRADA: a high-performance reconfigurable parallel architecture based on the dataflow model
International Journal of High Performance Systems Architecture
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