Cache and memory hierarchy design: a performance-directed approach
Cache and memory hierarchy design: a performance-directed approach
Building and Using a Highly Parallel Programmable Logic Array
Computer - Special issue on experimental research in computer architecture
Field-programmable gate arrays
Field-programmable gate arrays
IEEE Spectrum
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Presents the design of a variable width RAM (VaWiRAM) which will be extremely useful in building flexible memory systems. Principles of reconfigurability of programmable logic and programmable interconnect is incorporated into random access memories to achieve this flexibility. The chip can be reconfigured by setting a few configuration pins on the memory chip. A VaWiRAM reconfigurable between widths 1 and W/sub max/ can be constructed with the extra cost of W/sub max/-1 pass gates, W max/2- to -1 multiplexers, and [log/sub 2/[log/sub 2/(k)+1]] mode pins. The paper discusses the architecture of the proposed VaWiRAMs, and analyzes the trade-offs in their design.