Building and Using a Highly Parallel Programmable Logic Array
Computer - Special issue on experimental research in computer architecture
Programmable active memories: reconfigurable systems come of age
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parallelization of local BLAST service on workstation clusters
Future Generation Computer Systems
Database Allocation Strategies for Parallel BLAST Evaluation on Clusters
Distributed and Parallel Databases
TurboBLAST(r): A Parallel Implementation of BLAST Built on the TurboHub
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
A Reconfigurable Extension to the Network Interface of Beowulf Clusters
CLUSTER '01 Proceedings of the 3rd IEEE International Conference on Cluster Computing
Efficient Data Access for Parallel BLAST
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 01
RC-BLAST: Towards a Portable, Cost-Effective Open Source Hardware Implementation
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 7 - Volume 08
Automatic Mapping of Multiple Applications to Multiple Adaptive Computing Systems
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
IEEE Transactions on Parallel and Distributed Systems
Proceedings of the 2006 ACM/IEEE conference on Supercomputing
Parallel genomic sequence-search on a massively parallel system
Proceedings of the 4th international conference on Computing frontiers
A General Reconfigurable Architecture for the BLAST Algorithm
Journal of VLSI Signal Processing Systems
Biosequence Similarity Search on the Mercury System
Journal of VLSI Signal Processing Systems
Maxwell - a 64 FPGA Supercomputer
AHS '07 Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems
FCCM '07 Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Single pass streaming BLAST on FPGAs
Parallel Computing
Semantics-based distributed I/O for mpiBLAST
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming
Semantic-based distributed i/o with the paramedic framework
HPDC '08 Proceedings of the 17th international symposium on High performance distributed computing
Massively parallel genomic sequence search on the Blue Gene/P architecture
Proceedings of the 2008 ACM/IEEE conference on Supercomputing
A Hardware Filesystem Implementation for High-Speed Secondary Storage
RECONFIG '08 Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs
Phoenix: A Runtime Environment for High Performance Computing on Chip Multiprocessors
PDP '09 Proceedings of the 2009 17th Euromicro International Conference on Parallel, Distributed and Network-based Processing
RC-BLASTn: Implementation and Evaluation of the BLASTn Scan Function
FCCM '09 Proceedings of the 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines
AIREN: A Novel Integration of On-Chip and Off-Chip FPGA Networks
FCCM '09 Proceedings of the 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines
Axel: a heterogeneous cluster with FPGAs and GPUs
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Scalability Studies of the BLASTn Scan and Ungapped Extension Functions
RECONFIG '09 Proceedings of the 2009 International Conference on Reconfigurable Computing and FPGAs
A hardware filesystem implementation with multidisk support
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
Parallel DNA sequence alignment on the cell broadband engine
PPAM'07 Proceedings of the 7th international conference on Parallel processing and applied mathematics
Programming framework for clusters with heterogeneous accelerators
ACM SIGARCH Computer Architecture News
Redsharc: a programming model and on-chip network for multi-core systems on a programmable chip
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
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The Reconfigurable Computing Cluster project is exploring novel parallel computing architectures in high performance computing with FPGA devices. Although there are no discrete microprocessors in the system, highly-integrated FPGAs (with embedded processors) are capable of hosting Linux-based systems and can run arbitrary MPI applications. This work present an investigation into accelerating I/O bound streaming applications through the coupling of custom computing cores, a hardware filesystem, and an integrated on-chip and off-chip network on the all-FPGA node cluster. Such an infrastructure enables productivity by minimizing hardware design while maintaining high performance. A hardware implementation of the BLASTn algorithm is used to demonstrate the performance gains and scalability of the custom computing cores across the Spirit cluster. Results show linear speedup across multiple nodes while supporting productivity by eliminating modifications to the original hardware core when scaling up to 512 parallel cores on the cluster.