Configuration prefetch for single context reconfigurable coprocessors
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
The Chimaera reconfigurable functional unit
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
An Instruction-Level Distributed Processor for Symmetric-Key Cryptography
IEEE Transactions on Parallel and Distributed Systems
The Instruction-Set Extension Problem: A Survey
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
| Hi-index | 0.00 |
Abstract: The paper considers reconfigurable computing for application-specific systems, with particular reference to mixed-technology chips. A VLIW "core" is augmented by means of Reconfigurable Functional Units (RFUs) and register files implemented via FPGA onto the same chip. The application is analyzed to extract segments of computation that could be usefully collapsed into complex instructions decoded and executed by the RFUs. Here, we focus on the problem of selecting the optimum extension to the native Instruction Set by means of the "best" segments of computation that will become complex instruction. In particular a genetic algorithm approach is introduced to analyze the population of candidates; modifications to the classic genetic operators are introduced to take into account the peculiarity of our problem. Applying the proposed methodology to some significant applications has validated the overall approach