Scheduling designs into a time-multiplexed FPGA
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Behavioral synthesis with systemC
Proceedings of the conference on Design, automation and test in Europe
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
High Performance Computing by Context Switching Reconfigurable Logic
Proceedings of the 16th European Simulation Multiconference on Modelling and Simulation 2002
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
High Performance DES Encryption in Virtex(tm) FPGAs Using Jbits(tm)
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
An optimal algorithm for minimizing run-time reconfiguration delay
ACM Transactions on Embedded Computing Systems (TECS)
Register Binding for FPGAs with Embedded Memory
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Efficient datapath merging for the overhead reduction of run-time reconfigurable systems
The Journal of Supercomputing
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High-level synthesis is becoming more popular as design densities keep increasing, especially in the ASIC design world. Although FPGA design follows ASIC design methodologies and FPGA densities are increasing too, programmable devices also offer the advantage of partial reconfiguration, which allows an algorithm to be partially mapped into a small and fixed FPGA device that can be reconfigured at run time, as the mapped application changes its requirements. This paper presents a novel resource constrained high-level synthesis scheduling heuristic, which utilizes reconfigurable datapath components. The resulting schedule can be shortened so as the gain in clock cycles can overcome the timing overhead of reconfiguration. The main advantage of the proposed methodology is that through run time reconfiguration, more complicated algorithms can be mapped into smaller devices without speed degradation.