A high-performance microarchitecture with hardware-programmable functional units
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Communications of the ACM
Optimal Circuits for Parallel Multipliers
IEEE Transactions on Computers
The Chimaera reconfigurable functional unit
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Highly flexible multi-mode system synthesis
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
EURASIP Journal on Applied Signal Processing
Integration, the VLSI Journal
Construction of dual mode components for reconfiguration aware high-level synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
High-level synthesis with reconfigurable datapath components
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
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