Compatibility path based binding algorithm for interconnect reduction in high level synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
High-level synthesis with reconfigurable datapath components
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
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The trend in new state-of-the-art FPGAs is to have large amounts of on-chip embedded memory blocks. These memory blocks are used to hold the input/output data for various applications. Existing register binding techniques in high-level synthesis aim at minimizing the storage requirements of circuits by sharing variables among registers and thus minimizing the required number of registers for a specific design. In this paper, a new technique is proposed that makes use of the existing embedded memory blocks and maps variables to these blocks. The proposed memory binding approach gives considerable performance increase over the existing register binding techniques. The memory binding technique resulted in up to 57% savings in the total chip area (number of Logic Cells/Elements occupied on the FPGA) over the old register binding techniques for a small resource bag and up to 6% savings for a large resource bag.