Knapsack problems: algorithms and computer implementations
Knapsack problems: algorithms and computer implementations
Power management in high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An FPGA implementation and performance evaluation of the Serpent block cipher
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Introduction to algorithms
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
A stream compiler for communication-exposed architectures
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Fast Template Placement for Reconfigurable Computing Systems
IEEE Design & Test
Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures
Proceedings of the tenth international symposium on Hardware/software codesign
Automated target recognition on SPLASH 2
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
A Methodology for Task Based Partitioning and Scheduling of Dynamically Reconfigurable Systems
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Hardware-Software Codesign and Parallel Implementation of a Golomb Ruler Derivation Engine
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Designing an Operating System for a Heterogeneous Reconfigurable SoC
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Media Processing Applications on the Imagine Stream Processor
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Online Scheduling and Placement of Real-time Tasks to Partially Reconfigurable Devices
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
A design flow for partially reconfigurable hardware
ACM Transactions on Embedded Computing Systems (TECS)
An efficient algorithm for finding empty space for online FPGA placement
Proceedings of the 41st annual Design Automation Conference
Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks
IEEE Transactions on Computers
Guest editorial: Special issue on models and methodologies for co-design of embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Task Scheduling in a Finite-Resource, Reconfigurable Hardware/Software Codesign Environment
INFORMS Journal on Computing
Optimal Free-Space Management and Routing-Conscious Dynamic Placement for Reconfigurable Devices
IEEE Transactions on Computers
Energy minimization with soft real-time and DVS for uniprocessor and multiprocessor embedded systems
Proceedings of the conference on Design, automation and test in Europe
Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Cost minimization while satisfying hard/soft timing constraints for heterogeneous embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hardware task scheduling and placement in operating systems for dynamically reconfigurable SoC
Journal of Embedded Computing - Selected papers of EUC 2005
Dynamic and leakage energy minimization with soft real-time loop scheduling and voltage assignment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Efficient heuristic algorithms for path-based hardware/software partitioning
Mathematical and Computer Modelling: An International Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Measuring the Gap Between FPGAs and ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Reconfigurable computing systems have been used widely in various areas due to their attractive features in low-power and high-precision. However, how to increase utilization and throughput while reducing configuration and execution time overheads on large-scale data has become a great challenge for reconfigurable computing systems. In this paper, we employ a directed acyclic graph (DAG) to represent the tasks in an application. With considerations of task dependencies and resource constraints that are not sufficiently studied in literature, we propose two clustering scheduling strategies to reduce the number of configurations and the execution time of applications, while enhancing the utilization of field programmable gate array (FPGA) devices: One is a heuristic scheduling strategy and the other is a dynamic programming scheduling strategy. Experimental results indicate that our dynamic programming scheduling strategy can significantly reduce the number of configurations and improve the FPGA utilization, compared to the heuristic scheduling strategy.