Differential cryptanalysis of the data encryption standard
Differential cryptanalysis of the data encryption standard
Linear cryptanalysis method for DES cipher
EUROCRYPT '93 Workshop on the theory and application of cryptographic techniques on Advances in cryptology
Constructing Symmetric Ciphers Using the CAST Design Procedure
Designs, Codes and Cryptography - Special issue: selected areas in cryptography I
An FPGA implementation and performance evaluation of the Serpent block cipher
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
A High Performance Reconfigurable Elliptic Curve Processor for GF(2m)
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
An Energy Efficient Reconfigurable Public-Key Cryptograhpy Processor Architecture
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
Energy scalable reconfigurable cryptographic hardware for portable applications
Energy scalable reconfigurable cryptographic hardware for portable applications
A new method for known plaintext attack of FEAL cipher
EUROCRYPT'92 Proceedings of the 11th annual international conference on Theory and application of cryptographic techniques
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In this paper we propose an integrated hardware/ software methodology for the implementation of dynamically reconfigurable cryptoalgorithms with good security properties, on Field Programmable Gate Arrays (FPGAs): we start with a specific cryptoalgorithm implemented on the FPGA and then enable the modification of the only element of the algorithm that lets intact its structure, the substitution boxes. Since the properties of the s-boxes largely determine the properties of the cryptoalgorithm, we provide the architecture of a CAST-128 based cryptoalgorithm whose s-box construction methodology results in s-boxes with good properties. We map this architecture on ATMEL's innovative processor+FPGA chip FPSLIC驴 where the cryptoalgorithm is implemented on the FPGA part while the s-box construction algorithm runs on the processor part (AVR). The result is a one chip fast and secure cryptoalgorithm than can reconfigure itself at run time, either autonomously at regular time intervals or upon receipt of an external signal in order to hinder or confuse suspected cryptanalytic efforts.