Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Performance analysis of low-power 1-Bit CMOS full adder cells
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The Design of Rijndael
Architectures and VLSI Implementations of the AES-Proposal Rijndael
IEEE Transactions on Computers
An ASIC Implementation of the AES SBoxes
CT-RSA '02 Proceedings of the The Cryptographer's Track at the RSA Conference on Topics in Cryptology
A Compact Rijndael Hardware Architecture with S-Box Optimization
ASIACRYPT '01 Proceedings of the 7th International Conference on the Theory and Application of Cryptology and Information Security: Advances in Cryptology
Efficient Rijndael Encryption Implementation with Composite Field Arithmetic
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
An Optimized S-Box Circuit Architecture for Low Power AES Design
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
A Highly Regular and Scalable AES Hardware Architecture
IEEE Transactions on Computers
Power-efficient ASIC synthesis of cryptographic sboxes
Proceedings of the 14th ACM Great Lakes symposium on VLSI
A 10-Gbps full-AES crypto design with a twisted BDD S-box architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-speed VLSI architectures for the AES algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast composite field S-box architectures for advanced encryption standard
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Area, delay, and power characteristics of standard-cell implementations of the AES S-Box
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
Using Normal Bases for Compact Hardware Implementations of the AES S-Box
SCN '08 Proceedings of the 6th international conference on Security and Cryptography for Networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
692-nW advanced encryption standard (AES) on a 0.13-µm CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new combinational logic minimization technique with applications to cryptology
SEA'10 Proceedings of the 9th international conference on Experimental Algorithms
A systematic evaluation of compact hardware implementations for the rijndael s-box
CT-RSA'05 Proceedings of the 2005 international conference on Topics in Cryptology
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
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The Substitution box (S-Box) forms the core building block of any hardware implementation of the Advanced Encryption Standard (AES) algorithm as it is a non-linear structure requiring multiplicative inversion. This paper presents a full custom CMOS design of S-Box/Inversion S-Box (Inv S-Box) with low power GF (2^8) Galois Field inversions based on polynomial basis, using composite field arithmetic. The S-Box/Inv S-Box utilizes a novel low power 2-input XOR gate with only six devices to achieve a compact module implemented in 65nm IBM CMOS technology. The area of the core circuit is only about 288@mm^2 as a result of this transistor level optimization. The hardware cost of the S-Box/Inv S-Box is about 158 logic gates equivalent to 948 transistors with a critical path propagation delay of 7.322ns enabling a throughput of 130 Mega-SubBytes per second. This design indicates a power dissipation of only around 0.09@mW using a 0.8V supply voltage, and, is suitable for applications such as RFID tags and smart cards which require low power consumption with a small silicon die. The proposed implementation compares favorably with other existing S-Box designs.