A fast algorithm for computing multiplicative inverses in GF(2m) using normal bases
Information and Computation
A Compact Rijndael Hardware Architecture with S-Box Optimization
ASIACRYPT '01 Proceedings of the 7th International Conference on the Theory and Application of Cryptology and Information Security: Advances in Cryptology
Tight bounds for the multiplicative complexity of symmetric functions
Theoretical Computer Science
On the Shortest Linear Straight-Line Program for Computing Linear Forms
MFCS '08 Proceedings of the 33rd international symposium on Mathematical Foundations of Computer Science
Faster and Timing-Attack Resistant AES-GCM
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Consecutive S-box lookups: a timing attack on SNOW 3G
ICICS'10 Proceedings of the 12th international conference on Information and communications security
Synthesizing shortest linear straight-line programs over GF(2) using SAT
SAT'10 Proceedings of the 13th international conference on Theory and Applications of Satisfiability Testing
Billion-gate secure computation with malicious adversaries
Security'12 Proceedings of the 21st USENIX conference on Security symposium
CT-RSA'13 Proceedings of the 13th international conference on Topics in Cryptology
Faster secure two-party computation with less memory
Proceedings of the 8th ACM SIGSAC symposium on Information, computer and communications security
Minimalist security and privacy schemes based on enhanced AES for integrated WISP sensor networks
International Journal of Communication Networks and Distributed Systems
Low-power compact composite field AES S-Box/Inv S-Box design in 65nm CMOS using Novel XOR Gate
Integration, the VLSI Journal
PICCO: a general-purpose compiler for private distributed computation
Proceedings of the 2013 ACM SIGSAC conference on Computer & communications security
From oblivious AES to efficient and secure database join in the multiparty setting
ACNS'13 Proceedings of the 11th international conference on Applied Cryptography and Network Security
PCF: a portable circuit format for scalable two-party secure computation
SEC'13 Proceedings of the 22nd USENIX conference on Security
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A new technique for combinational logic optimization is described. The technique is a two-step process. In the first step, the non-linearity of a circuit – as measured by the number of non-linear gates it contains – is reduced. The second step reduces the number of gates in the linear components of the already reduced circuit. The technique can be applied to arbitrary combinational logic problems, and often yields improvements even after optimization by standard methods has been performed. In this paper we show the results of our technique when applied to the S-box of the Advanced Encryption Standard (AES [6]). This is an experimental proof of concept, as opposed to a full-fledged circuit optimization effort. Nevertheless the result is, as far as we know, the circuit with the smallest gate count yet constructed for this function. We have also used the technique to improve the performance (in software) of several candidates to the Cryptographic Hash Algorithm Competition. Finally, we have experimentally verified that the second step of our technique yields significant improvements over conventional methods when applied to randomly chosen linear transformations.