Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
The Design of Rijndael
Efficient Algorithms for Elliptic Curve Cryptosystems
CRYPTO '97 Proceedings of the 17th Annual International Cryptology Conference on Advances in Cryptology
Link Layer Security for SAHN Protocols
PERCOMW '05 Proceedings of the Third IEEE International Conference on Pervasive Computing and Communications Workshops
A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
A Totally Self-Checking S-box Architecture for the Advanced Encryption Standard
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors
IEEE Transactions on Computers
Reconfigurable system for high-speed and diversified AES using FPGA
Microprocessors & Microsystems
Fast composite field S-box architectures for advanced encryption standard
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Design of an ultra high speed AES processor for next generation IT security
Computers and Electrical Engineering
Accelerating AES using instruction set extensions for elliptic curve cryptography
ICCSA'05 Proceedings of the 2005 international conference on Computational Science and Its Applications - Volume Part II
Low-power compact composite field AES S-Box/Inv S-Box design in 65nm CMOS using Novel XOR Gate
Integration, the VLSI Journal
| Hi-index | 0.00 |
In this brief, we present a high-speed AES IP-core, which runs at 880 MHz on a 0.13-µm CMOS standard cell library, and which achieves over 10-Gbps throughput in all encryption modes, including cipher block chaining (CBC) mode. Although the CBC mode is the most widely used and important, achieving such high throughput was difficult because pipelining and/or loop unrolling techniques cannot be applied. To reduce the propagation delays of the S-Box, the slowest function block, we developed a special circuit architecture that we call twisted-binary decision diagram (BDD), where the fanout of signals is distributed in the S-Box circuit. Our S-Box is 1.5 to 2 times faster than the conventional S-Box implementations. The T-Box algorithm, which merges the S-Box and another primitive function (MixColumns) into a single function, is also used for an additional speedup.