Cryptography and network security (2nd ed.): principles and practice
Cryptography and network security (2nd ed.): principles and practice
AES Implementation on FPGA: Time - Flexibility Tradeoff
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Cryptography on a Speck of Dust
Computer
IDEA and AES, two cryptographic algorithms implemented using partial and dynamic reconfiguration
Microelectronics Journal
Design of an ultra high speed AES processor for next generation IT security
Computers and Electrical Engineering
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Today most research involving the execution of the Advanced Encryption Standard (AES) algorithm falls into three areas: ultra-high-speed encryption, very low power consumption, and algorithmic integrity. This study's focus is on how to lower the power consumption of an FPGA-based encryption scheme with minimum effect on performance. Three novel FPGA schemes are introduced and evaluated. These schemes are compared in terms of architectural and performance differences, as well as the power consumption rates. The results show that the proposed schemes are able to reduce the logic and signal power by 60% and 27%, respectively on a Virtex 2 Pro FPGA while maintaining a high level of throughput.