A proposal for a new block encryption standard
EUROCRYPT '90 Proceedings of the workshop on the theory and application of cryptographic techniques on Advances in cryptology
A Simplified Architecture for Modulo (2n + 1) Multiplication
IEEE Transactions on Computers
Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Handbook of Applied Cryptography
Handbook of Applied Cryptography
Tradeoffs in Parallel and Serial Implementations of the International Data Encryption Algorithm IDEA
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
IDEA: A Cipher For Multimedia Architectures?
SAC '98 Proceedings of the Selected Areas in Cryptography
Efficient VLSI Implementation of Modulo (2^n=B11) Addition and Multiplication
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design
Markov ciphers and differential cryptanalysis
EUROCRYPT'91 Proceedings of the 10th annual international conference on Theory and application of cryptographic techniques
A fully pipelined memoryless 17.8 Gbps AES-128 encryptor
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Efficient Diminished-1 Modulo 2^n+1 Multipliers
IEEE Transactions on Computers
IDEA and AES, two cryptographic algorithms implemented using partial and dynamic reconfiguration
Microelectronics Journal
64-bit Block ciphers: hardware implementations and comparison analysis
Computers and Electrical Engineering
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IDEA (International Data Encryption Algorithm) is one of the strongest secret-key block ciphers. The algorithm processes data in 16-bit subblocks and can be fully pipelined. The implementation of a fully pipelined IDEA algorithm achieves a clock rate of 105.9 MHz on Xilinx' XCV1000E-6BG560 FPGA of the Virtex-E device family. The implementation uses 18105 logic cells and achieves a throughput of 6.78 Gbps with a latency of 132clo ck cycles.