Optimally scaling permutation routing on reconfigurable linear arrays with optical buses
Journal of Parallel and Distributed Computing
Time-Division Optical Communications in Multiprocessor Arrays
IEEE Transactions on Computers
Implementation of Near Shannon Limit Error-Correcting Codes Using Reconfigurable Hardware
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
(C) Integer Sorting and Routing in Arrays with Reconfigurable Optical Buses
ICPP '96 Proceedings of the Proceedings of the 1996 International Conference on Parallel Processing - Volume 2
Dynamic Reconfiguration: Architectures and Algorithms (Series in Computer Science (Kluwer Academic/Plenum Publishers).)
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In this paper we propose a constant-time parallel algorithm for implementing the message-passing decoder of LDPC codes on a two dimensional RMesh, trying to keep the number of processors small. The R-Mesh provides dynamic reconfiguration, hardware reuse, and flexibility to problem changes. To decode a different code, we may simply set up the required connections between the bit-nodes and check-nodes by modifying the initialization phase of the R-Mesh algorithm. No extra wiring or hardware changes are required, as compared to other existing approaches. Moreover, the same hardware can implement the decoder in both probability and logarithm domains. We illustrate that the R-Mesh is an efficient model for parallel implementation of the decoder in terms of time complexity, flexibility to problem changes and simplicity of routing messages.