An FPGA Interpreter with Virtual Hardware Management

Authors:
Oliver Diessel;Usama Malik
Affiliations:
-;-
Venue:
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Year:
2002

Citing 4
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Abstract

This paper describes the design of an interpreter that overcomes FPGA resource limitations for a class of control-oriented circuits by automatically partitioning, elaborating, and loading circuit components as directed by their execution. By providing a virtual hardware management facility, this enables us to implement large systems, specified in Circal, on small FPGA chips.