CIRCAL and the representation of communication, concurrency, and time
ACM Transactions on Programming Languages and Systems (TOPLAS) - Lecture notes in computer science Vol. 174
Communicating sequential processes
Communicating sequential processes
Communication and concurrency
Formal Specification and Verification of Digital Systems
Formal Specification and Verification of Digital Systems
A Highly Parallel FPL-Based Machine and Its Formal Verification
Selected papers from the Second International Workshop on Field-Programmable Logic and Applications, Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping
Compiling Process Algebraic Descriptions into Reconfigurable Logic
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Towards a Provably Correct Hardware Implementation of Occam
CHARME '93 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
A Model for Dynamic Adaptation in Reconfigurable Hardware Systems
EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Implementing C Algorithms in Reconfigurable Hardware Using C2Verilog
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
An FPGA Interpreter with Virtual Hardware Management
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
| Hi-index | 0.00 |
High-level, behavioural language specification is seen as a significant strategy for overcoming the complexity of designing useful and interesting reconfigurable computing applications. However, appropriate frameworks for the design of behaviourally specified systems are still being sought. We are investigating behavioural language and compiler design based on the Circal process algebra, which is a natural framework within which to describe the concurrent activity of reconfigurable logic circuits. In this paper we describe an FPGA interpreter that exploits the inherent concurrency, hierarchy, and modularity of Circal and its circuit realization to automatically manage hardware virtualization. The techniques employed by the interpreter may be used to overcome resource limitations and adapt circuits to changing application needs at run time.