Implementing Condition/Event Nets in the Circal Process Algebra
FASE '02 Proceedings of the 5th International Conference on Fundamental Approaches to Software Engineering
Compiling Process Algebraic Descriptions into Reconfigurable Logic
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Process Algebra versus Axiomatic Specification of a Real-Time Protocol
AMAST '00 Proceedings of the 8th International Conference on Algebraic Methodology and Software Technology
A Methodology for the Formal Analysis of Asynchronous Micropipelines
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Behavioural Language Compilation with Virtual Hardware Management
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Towards a User-Friendly Design and Verification Environment
SEW '02 Proceedings of the 27th Annual NASA Goddard Software Engineering Workshop (SEW-27'02)
From process algebra to visual language
CRPIT '02 Proceedings of the conference on Application and theory of petri nets: formal methods in software engineering and defence systems - Volume 12
Visual security protocol modeling
NSPW '05 Proceedings of the 2005 workshop on New security paradigms
A formalism for visual security protocol modeling
Journal of Visual Languages and Computing
Formalization of a parameterized parallel adder within the coq theorem prover
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reusing hardware components with single-state processes
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Properties as processes: their specification and verification
FORTE'05 Proceedings of the 25th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
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From the Publisher:The necessity of producing error-free integrated circuits follows from the cost and inconvenience which ensue if errors are found to be present in a completed circuit. As a result of this need and of the problems associated with simulation methods,formal verification techniques are now emerging as a realistic alternative. This book develops in detail two complementary approaches to hardware verification and is intended to be a standalone introduction to the subject. These involve the use of higher order logic and process algebras respectively. The material is divided into three parts. The first concerns itself with the role of hardware specification,and specification languages,in the formal verification process. The traditional validation technique,that of simulation,is discussed and is contrasted with formal hardware verification. Finally,the third part presents a particular process calculus as an appropriate formalism for rigorous design analysis. In both the second and the third parts the fundamental concepts of logic and process calculi are introduced and techniques for using them are presented by the use of an extensive set of examples.