Principles of parameterized programming
Software reusability: vol. 1, concepts and models
PARIS: a system for reusing partially interpreted schemas
Software reusability: vol. 1, concepts and models
Communication and Concurrency
Formal Specification and Verification of Digital Systems
Formal Specification and Verification of Digital Systems
Ella 2000: A Language for Electronic System Design
Ella 2000: A Language for Electronic System Design
MENU - An Example for the Systematic Reuse of Specifications
ESEC '89 Proceedings of the 2nd European Software Engineering Conference
A foundation for formal reuse of hardware
CHARME '95 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Formal support for the ELLA hardwar description language
CHARME '95 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
The Linear Time-Branching Time Spectrum (Extended Abstract)
CONCUR '90 Proceedings of the Theories of Concurrency: Unification and Extension
The Linear Time - Branching Time Spectrum II
CONCUR '93 Proceedings of the 4th International Conference on Concurrency Theory
Concurrency and Automata on Infinite Sequences
Proceedings of the 5th GI-Conference on Theoretical Computer Science
"On the Fly" Verification of Behavioural Equivalences and Preorders
CAV '91 Proceedings of the 3rd International Workshop on Computer Aided Verification
An algebraic definition of simulation between programs
IJCAI'71 Proceedings of the 2nd international joint conference on Artificial intelligence
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The interest of reuse existing components lies on the idea of reducing the efforts to develop new systems. The best reuse is achieved as no new components are required to be built. Most time, however, this ideal case is not feasible, and at least part of the system is required to be designed. For such cases, the new elements being constructed must be as simple as possible in order to take advantages of the reuse principles. This paper presents a technique to reuse synchronous hardware components as a single level combinational circuit is required to be built. A synchronous process algebra is used to represent hardware components.