Four-phase micropipeline latch control circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Communication and Concurrency
Formal Specification and Verification of Digital Systems
Formal Specification and Verification of Digital Systems
The Theory and Practice of Concurrency
The Theory and Practice of Concurrency
Dynamic Logic in Four-Phase Micropipelines
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Integrating the Verification of Timing, Performance and Correctness Properties of Concurrent Systems
CSD '98 Proceedings of the 1998 International Conference on Application of Concurrency to System Design
A comparison of performance evaluation process algebra and generalized stochastic Petri nets
PNPM '95 Proceedings of the Sixth International Workshop on Petri Nets and Performance Models
Implementing Condition/Event Nets in the Circal Process Algebra
FASE '02 Proceedings of the 5th International Conference on Fundamental Approaches to Software Engineering
Towards a User-Friendly Design and Verification Environment
SEW '02 Proceedings of the 27th Annual NASA Goddard Software Engineering Workshop (SEW-27'02)
From process algebra to visual language
CRPIT '02 Proceedings of the conference on Application and theory of petri nets: formal methods in software engineering and defence systems - Volume 12
SIFA: a tool for evaluation of high-grade security devices
ACISP'05 Proceedings of the 10th Australasian conference on Information Security and Privacy
Properties as processes: their specification and verification
FORTE'05 Proceedings of the 25th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
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In this paper we present a process algebra approach for the integrated verification of correctness and performance in concurrent systems. The verification procedure is entirely performed within the Circal process algebra, without any recourse to other formalisms. Performance is characterised in terms of logical properties, which do not incorporate explicit time. Such properties are then interpreted in terms of degree of parallelism and allow the quantitative evaluation of the throughput of the system. The approach has been applied to two four-phase handshaking protocols, which are motivated by the implementation of the AMULET2 asynchronous RISC processor. Both correctness and performance properties are captured in the same verification framework and automatically proved using the Circal System.