Real-time embedded software design for mobile and ubiquitous systems

  • Authors:

  • Pao-Ann Hsiung;Shang-Wei Lin;Chin-Chieh Hung;Jih-Ming Fu;Chao-Sheng Lin;Cheng-Chi Chiang;Kuo-Cheng Chiang;Chun-Hsien Lu;Pin-Hsien Lu

  • Affiliations:

  • Department of Computer Science and Information Engineering, National Chung-Cheng University, Chiayi, Taiwan, ROC;Department of Computer Science and Information Engineering, National Chung-Cheng University, Chiayi, Taiwan, ROC;Department of Computer Science and Information Engineering, National Chung-Cheng University, Chiayi, Taiwan, ROC;Department of Computer Science and Information Engineering, National Chung-Cheng University, Chiayi, Taiwan, ROC;Department of Computer Science and Information Engineering, National Chung-Cheng University, Chiayi, Taiwan, ROC;Department of Computer Science and Information Engineering, National Chung-Cheng University, Chiayi, Taiwan, ROC;Department of Computer Science and Information Engineering, National Chung-Cheng University, Chiayi, Taiwan, ROC;Department of Computer Science and Information Engineering, National Chung-Cheng University, Chiayi, Taiwan, ROC;Department of Computer Science and Information Engineering, National Chung-Cheng University, Chiayi, Taiwan, ROC

  • Venue:
  • EUC'07 Proceedings of the 2007 international conference on Embedded and ubiquitous computing
  • Year:
  • 2007

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Abstract

Currently available application frameworks that target at the automatic design of real-time embedded software are poor in integrating functional and non-functional requirements for mobile and ubiquitous systems. In this work, we present the internal architecture and design flow of a newly proposed framework called Verifiable Embedded Real-Time Application Framework (VERTAF), which integrates three techniques namely software component-based reuse, formal synthesis, and formal verification. The proposed architecture for VERTAF is component-based which allows plug-and-play for the scheduler and the verifier. The architecture is also easily extensible because reusable hardware and software design components can be added. Application examples developed using VERTAF demonstrate significantly reduced relative design effort, which shows how high-level reuse of software components combined with automatic synthesis and verification increases design productivity.