Automating Formal Modular Verification of Asynchronous Real-Time Embedded Systems

  • Authors:
  • Pao-Ann Hsiung;Shu-Yu Cheng

  • Affiliations:
  • -;-

  • Venue:
  • VLSID '03 Proceedings of the 16th International Conference on VLSI Design
  • Year:
  • 2003

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Abstract

Most verification tools and methodologies such as modelchecking, equivalence checking, hardware verification, softwareverification, and hardware-software coverification oftenflatten out the behavior of a target system before verification.Inherent modularities, either explicit or implicit,functional or structural, are not exploited by these tools andalgorithms. In this work, we show how assume-guaranteereasoning (AGR) can be used for such exploitations by integratingAGR into a verification tool. Targeting at real-timeembedded systems, we propose procedures to automaticallygenerate assumptions, guarantees, and time constraints,which otherwise require manual efforts and humancreativity. Through a complex but comprehensible real-timeembedded system example such as a Vehicle Parking ManagementSystem (VPMS), we illustrate the feasibility of theAGR approach and the extremely large reduction possiblein state-space sizes when AGR is applied. Due to AGR, wealso found five errors in the VPMS design using much lesserCPU time and memory space than possible without AGR.