IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
Formal Methods in System Design - Special issue on The First Federated Logic Conference (FLOC'96), part II
Model checking
Bandera: extracting finite-state models from Java source code
Proceedings of the 22nd international conference on Software engineering
Automated Refinement Checking for Asynchronous Processes
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
MOCHA: Modularity in Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
You Assume, We Guarantee: Methodology and Case Studies
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Alternating-time Temporal Logic
FOCS '97 Proceedings of the 38th Annual Symposium on Foundations of Computer Science
Alternating-time temporal logic
Journal of the ACM (JACM)
Heuristics for Hierarchical Partitioning with Application to Model Checking
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Hierarchical Hybrid Modeling of Embedded Systems
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
Verifying Network Protocol Implementations by Symbolic Refinement Checking
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Synchronous and Bidirectional Component Interfaces
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Interface Compatibility Checking for Software Modules
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Automating Formal Modular Verification of Asynchronous Real-Time Embedded Systems
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Shared Variables Interaction Diagrams
Proceedings of the 16th IEEE international conference on Automated software engineering
Modular refinement of hierarchic reactive machines
ACM Transactions on Programming Languages and Systems (TOPLAS)
Model Checking C Programs Using F-SOFT
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Uniform random sampling of traces in very large models
Proceedings of the 1st international workshop on Random testing
Efficient SAT-based bounded model checking for software verification
Theoretical Computer Science
Solving games via three-valued abstraction refinement
Information and Computation
Design and verification of systems with exogenous coordination using Vereofy
ISoLA'10 Proceedings of the 4th international conference on Leveraging applications of formal methods, verification, and validation - Volume Part II
Hierarchical modeling and formal verification: an industrial case study using Reo and Vereofy
FMICS'11 Proceedings of the 16th international conference on Formal methods for industrial critical systems
Model checking strategic abilities of agents under incomplete information
ICTCS'05 Proceedings of the 9th Italian conference on Theoretical Computer Science
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Solving games via three-valued abstraction refinement
CONCUR'07 Proceedings of the 18th international conference on Concurrency Theory
Bounded planning for strategic goals with incomplete information and perfect recall
Proceedings of the 2013 international conference on Autonomous agents and multi-agent systems
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