“Sometimes” and “not never” revisited: on branching versus linear time temporal logic
Journal of the ACM (JACM) - The MIT Press scientific computation series
Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Limits for automatic verification of finite-state concurrent systems
Information Processing Letters
Reasoning about networks with many identical finite state processes
Information and Computation
A structural induction theorem for processes
Proceedings of the eighth annual ACM Symposium on Principles of distributed computing
Reasoning about systems with many processes
Journal of the ACM (JACM)
POPL '95 Proceedings of the 22nd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Better verification through symmetry
Formal Methods in System Design - Special issue on symmetry in automatic verification
Exploiting symmetry in temporal logic model checking
Formal Methods in System Design - Special issue on symmetry in automatic verification
Formal Methods in System Design - Special issue on symmetry in automatic verification
Verification engineering: a future profession
PODC '97 Proceedings of the sixteenth annual ACM symposium on Principles of distributed computing
Utilizing symmetry when model-checking under fairness assumptions: an automata-theoretic approach
ACM Transactions on Programming Languages and Systems (TOPLAS)
Computer-aided Verification
A New Approach for the Verification of Cache Coherence Protocols
IEEE Transactions on Parallel and Distributed Systems
Model Checking Real-Time Properties of Symmetric Systems
MFCS '98 Proceedings of the 23rd International Symposium on Mathematical Foundations of Computer Science
From Asymmetry to Full Symmetry: New Techniques for Symmetry Reduction in Model Checking
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Verification of Infinite State Systems by Compositional Model Checking
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Verifying Properties of Large Sets of Processes with Network Invariants
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Specification and verification of concurrent systems in CESAR
Proceedings of the 5th Colloquium on International Symposium on Programming
Exploiting Symmetry When Verifying Transitor-Level Circuits by Symbolic Trajectory Evaluation
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Verification of Parameterized Bus Arbitration Protocol
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Automatic Verification of Parameterized Synchronous Systems (Extended Abstract)
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Parametrized Verification of Linear Networks Using Automata as Invariants
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
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Model checking is an automatic method for verifying correctness of reactive programs. Originally proposed as part of the dissertation work of the author, model checking is based on efficient algorithms searching for the presence or absence of temporal patterns. In fact, model checking rests on a theoretical foundation of basic principles from modal logic, lattice theory, as well as automata theory that permits program reasoning to be completely automated in principle and highly automated in practice. Because of this automation, the practice of model checking is nowadays well-developed, and the range of successful applications is growing. Model checking is used by most major hardware manufacturers to verify microprocessor circuits, while there have been promising advances in its use in software verification as well. The key obstacle to applicability of model checking is, of course, the state explosion problem. This paper discusses part of our ongoing research program to limit state explosion. The relation of theory to practice is also discussed.