Reasoning about parallel architectures
Reasoning about parallel architectures
Formal specification of abstract memory models
Proceedings of the 1993 symposium on Research on integrated systems
The SPARC architecture manual (version 9)
The SPARC architecture manual (version 9)
Using “test model-checking” to verify the Runway-PA8000 memory model
Proceedings of the tenth annual ACM symposium on Parallel algorithms and architectures
Alpha Architecture Reference Manual
Alpha Architecture Reference Manual
A New Approach for the Verification of Cache Coherence Protocols
IEEE Transactions on Parallel and Distributed Systems
The 'Test Model-Checking' Approach to the Verification of Formal Memory Models of Multiprocessors
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Automatic Datapath Abstraction In Hardware Systems
Proceedings of the 7th International Conference on Computer Aided Verification
Better Verification Through Symmetry
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
Formal design and verification methods for shared memory systems
Formal design and verification methods for shared memory systems
How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
IEEE Transactions on Computers
A Specification and Verification Framework for Developing Weak Shared Memory Consistency Protocols
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
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The problem of verifying finite-state models of shared memory multiprocessor coherence protocols for conformance to weaker memory consistency models is examined. We start with W.W. Collier's architectural testing methods and extend it in several non-trivial ways in order to be able to handle weak er memory models. This, our first contribution, presents the construction of architectural testing programs similar to those constructed by Collier (e.g. the ARCHTEST suite) suited for weaker memory models. Our own primary emphasis has, how ever, been to adapt these methods to the realm of model-chec king. In an earlier effort (joint work with Nalumasu and Mokkedem), we had demonstrated how to adapt Collier's architectural testing methods to model-checking. Our verification approach consisted of abstracting executions that violate memory orderings into a fixed collection of automata (called Test Automata) that depend only on the memory model. The main advantage of this approach, called Test Model-chec king, is that the test automata remain fixed during the iterative design cycle when different coherence protocols that (presumably) implement a given memory model are being compared for performance. This facilitates 'push-button' reverification when each new protocol is being considered. Our second contribution is to extend the methods of constructing test automata to be able to handle architectural tests for weaker memory models. After reviewing prior work, in this paper we mainly focus on architectural tests for weaker memory models and the new abstraction methods there of to construct test automata for weaker memory models.