Access ordering and coherence in shared memory multiprocessors
Access ordering and coherence in shared memory multiprocessors
The existence of refinement mappings
Theoretical Computer Science
Reasoning about parallel architectures
Reasoning about parallel architectures
Alpha architecture reference manual
Alpha architecture reference manual
The power of processor consistency
SPAA '93 Proceedings of the fifth annual ACM symposium on Parallel algorithms and architectures
The SPARC architecture manual (version 9)
The SPARC architecture manual (version 9)
IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
Memory consistency and event ordering in scalable shared-memory multiprocessors
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Piranha: a scalable architecture based on single-chip multiprocessing
Proceedings of the 27th annual international symposium on Computer architecture
Time, clocks, and the ordering of events in a distributed system
Communications of the ACM
Parallelizing the Murϕ Verifier
Formal Methods in System Design - Special issue on CAV '97
Verification Methods for Weaker Shared Memory Consistency Models
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Cache Coherence Verification with TLA+
FM '99 Proceedings of the Wold Congress on Formal Methods in the Development of Computing Systems-Volume II
The 'Test Model-Checking' Approach to the Verification of Formal Memory Models of Multiprocessors
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Verifying Sequential Consistency on Shared-Memory Multiprocessor Systems
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Model-checking of correctness conditions for concurrent objects
LICS '96 Proceedings of the 11th Annual IEEE Symposium on Logic in Computer Science
Using Lamport Clocks to Reason About Relaxed Memory Models
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
Towards a Formal Model of Shared Memory Consistency for Intel Itanium(tm)
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Computer-assisted analysis of multiprocessor memory systems
Computer-assisted analysis of multiprocessor memory systems
How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
IEEE Transactions on Computers
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A specification and verification methodology for Distributed Shared Memory consistency protocols implementing weak shared memory consistency models is proposed. Our approach uniformly describes a wide range of weak memory models in terms of a single concept--the visibility order of loads, stores, and synchronization operations, as perceived by all the processors. A given implementation is correct with respect to a weak memory model if it produces executions satisfying the visibility order for that memory model. Given an implementation, the designer annotates it with events from the visibility order, and runs reachability analysis to verify it against a specification that is also similarly annotated. A specification is obtained in two stages: first, the designer reverse engineers an intermediate abstraction from the implementation by replacing the coherence network with a logically equivalent concurrent data structure. The replacement is selected in a standard way, depending almost exclusively on the memory model. Verification of the intermediate abstraction against a visibility order specification can be accomplished using theorem-proving. The methodology was applied to four snoopy-bus protocols implementing aspects of the Alpha and Itanium memory models, with encouraging results.