Sequential circuit verification using symbolic model checking
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
The Stanford Dash Multiprocessor
Computer
Active messages: a mechanism for integrated communication and computation
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
LogP: towards a realistic model of parallel computation
PPOPP '93 Proceedings of the fourth ACM SIGPLAN symposium on Principles and practice of parallel programming
Finite state machine verification on MIMD machines
EURO-DAC '92 Proceedings of the conference on European design automation
The Stanford FLASH multiprocessor
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures
Implementation of an efficient parallel BDD package
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Techniques for efficient formal verification using binary decision diagrams
Techniques for efficient formal verification using binary decision diagrams
Effects of communication latency, overhead, and bandwidth in a cluster architecture
Proceedings of the 24th annual international symposium on Computer architecture
State reduction methods for automatic formal verification
State reduction methods for automatic formal verification
A new scheme for memory-efficient probabilistic verification
IFIP TC6/ 6.1 international conference on formal description techniques IX/protocol specification, testing and verification XVI on Formal description techniques IX : theory, application and tools: theory, application and tools
Binary decision diagrams on network of workstation
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
On Limits and Possibilities of Automated Protocol Analysis
Proceedings of the IFIP WG6.1 Seventh International Conference on Protocol Specification, Testing and Verification VII
Using Magnatic Disk Instead of Main Memory in the Murphi Verifier
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Reliable Hashing without Collosion Detection
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
The Murphi Verification System
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Parallelizing the Murphi Verifier
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
A Distributed Partial Order Reduction Algorithm
FORTE '02 Proceedings of the 22nd IFIP WG 6.1 International Conference Houston on Formal Techniques for Networked and Distributed Systems
A Specification and Verification Framework for Developing Weak Shared Memory Consistency Protocols
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Efficiently generating test vectors with state pruning
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Parallel Randomized State-Space Search
ICSE '07 Proceedings of the 29th international conference on Software Engineering
Parallel test generation and execution with Korat
Proceedings of the the 6th joint meeting of the European software engineering conference and the ACM SIGSOFT symposium on The foundations of software engineering
Measuring and Evaluating Parallel State-Space Exploration Algorithms
Electronic Notes in Theoretical Computer Science (ENTCS)
Parallel symbolic execution for structural test generation
Proceedings of the 19th international symposium on Software testing and analysis
Distributed and predictable software model checking
VMCAI'11 Proceedings of the 12th international conference on Verification, model checking, and abstract interpretation
Parallelizing a symbolic compositional model-checking algorithm
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
Parallel and distributed model checking in eddy
SPIN'06 Proceedings of the 13th international conference on Model Checking Software
Supporting domain-specific state space reductions through local partial-order reduction
ASE '11 Proceedings of the 2011 26th IEEE/ACM International Conference on Automated Software Engineering
Evaluation of a simple, scalable, parallel best-first search strategy
Artificial Intelligence
System level formal verification via model checking driven simulation
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
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With the use of state and memory reduction techniques in verification by explicit state enumeration, runtime becomes a major limiting factor. We describe a parallel version of the explicit state enumeration verifier Murϕ for distributed memory multiprocessors and networks of workstations using the message passing paradigm. In experiments with three complex cache coherence protocols on an Sp2 multiprocessor and on a network of workstations at UC Berkeley, parallel Murϕ shows close to linear speedups, which are largely insensitive to communication latency and bandwidth. There is some slowdown with increasing communication overhead, for which a simple yet relatively accurate approximation formula is given. Techniques to reduce overhead and required bandwidth and to allow heterogeneity and dynamically changing load in the parallel machine are discussed, which we expect will allow good speedups when using conventional networks of workstations.