Temporal-logic theorem proving
Temporal-logic theorem proving
Model checking and abstraction
ACM Transactions on Programming Languages and Systems (TOPLAS)
A formal approach to determining parallel resource bindings: experience report
ICSE '94 Proceedings of the 16th international conference on Software engineering
A New Approach for the Verification of Cache Coherence Protocols
IEEE Transactions on Parallel and Distributed Systems
EDS: A Parallel Computer System for Advanced Information Processing
PARLE '92 Proceedings of the 4th International PARLE Conference on Parallel Architectures and Languages Europe
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The presence of an effective verification process at an earlier phase of the system development lifecycle will have a greater impact on productivity and product quality than a verification process at a later phase. The usual verification process at the later coding phases involves some form of testing. As high-level design cannot be tested in the same way as code, an option at that phase is some kind of formal verification. A process of verification is presented for the high-level design phase of an operating system development, where both rigorous and formal verification are used, and the rigorous directs the formal. The methodology is based on temporal logic. Formal proofs are manageable on an in-house theorem prover.