A Combinatorial Problem Related to Interleaved Memory Systems
Journal of the ACM (JACM)
Vector Computer Memory Bank Contention
IEEE Transactions on Computers
Memory contention for shared memory vector multiprocessors
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
The impact of distributions and disciplines on multiple processor systems
Communications of the ACM
Interference in multiprocessor computer systems with interleaved memory
Communications of the ACM
A simulation study of a multi-nodal communications network with contention
WSC '83 Proceedings of the 15th conference on Winter simulation - Volume 1
A study of interleaved memory systems by trace driven simulation
ANSS '76 Proceedings of the 4th symposium on Simulation of computer systems
Shared Cache for Multiple-Stream Computer Systems
IEEE Transactions on Computers
On the Effective Bandwidth of Parallel Memories
IEEE Transactions on Computers
An Optimal Algorithm for Scheduling Requests on Interleaved Memories for a Pipelined Processor
IEEE Transactions on Computers
| Hi-index | 48.26 |
A model of interleaved memory systems is presented, and the analysis of the model by Monte Carlo simulation is discussed. The simulations investigate the performance of various system structures, i.e. schemes for sending instruction and data requests to the memory system. Performance is measured by determining the distribution of the number of memory modules in operation during a memory cycle.An important observation from these investigations is that separately grouping instruction and data requests for memory can substantially increase the average number of memory modules in operation during a memory cycle. Results of the simulations and an analytical study are displayed for various system structures.