Interference in multiprocessor computer systems with interleaved memory
Communications of the ACM
The working set model for program behavior
Communications of the ACM
Memory organizations and their effectiveness for multiprocessing computers.
Memory organizations and their effectiveness for multiprocessing computers.
Effects of buffered memory requests in multiprocessor systems
SIGMETRICS '79 Proceedings of the 1979 ACM SIGMETRICS conference on Simulation, measurement and modeling of computer systems
Performance of cache-based multiprocessors
SIGMETRICS '81 Proceedings of the 1981 ACM SIGMETRICS conference on Measurement and modeling of computer systems
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The performance of various memory configurations for parallel-pipelined computer which execute multiple instruction streams on multiple data streams is investigated. For a parallel-pipelined processor of order (s,p), which consists of p parallel processors each of which is a pipelined processor with s degrees of multiprogramming, there can be up to s p memory requests in each instruction cycle. The memory, which consists of N(&equil;2n) identical memory modules, is organized such that there are l(&equil;2i) lines and m(&equil;2n−i) modules per line, where each module is characterized by the address cycle (address hold time)and memory cycle of a and c time units respectively. The performance which is affected by the memory interference problem is evaluated as a function of the memory configuration, (l, m), the module characteristics (a, c) and the processor order (s, p). Design considerations are discussed and an example given to illustrate possible design options.