Performance of memory configurations for parallel-pipelined computers
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
An analysis of the instruction execution rate in certain computer structures
An analysis of the instruction execution rate in certain computer structures
Analysis of Memory Interference in Multiprocessors
IEEE Transactions on Computers
Analysis of interleaved storage via a constant-service queuing system with Markov-chain-driven input
Journal of the ACM (JACM)
Memory access buffering in multiprocessors
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Memory Access Dependencies in Shared-Memory Multiprocessors
IEEE Transactions on Software Engineering
Buffered Banks in Multiprocessor Systems
IEEE Transactions on Computers
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A simulation model is developed and used to study the effect of buffering of memory requests on the performance of multiprocessor systems. A multiprocessor system is generalized as a parallel-pipelined processor of order (s,p), which consists of p parallel processors each of which is a pipelined processor with s degrees of multiprogramming, there can be up to s*p memory requests in each instruction cycle. The memory, which consists of N(&equil;2n) identical memory modules, is organized such that there are l(&equil;2i) lines and m(&equil;2n−i) identical memory modules, where each module is characterized by the address cycle (address hold time) and memory cycle of a and c time units respectively. Too large an l is undesirable in a multiprocessor system because of the cost of the processor-memory interconnection network. Hence, we will show how effective buffering can be used to reduce the system cost while effectively maintaining a high level of performance.