Interference in multiprocessor computer systems with interleaved memory
Communications of the ACM
An analysis of the instruction execution rate in certain computer structures
An analysis of the instruction execution rate in certain computer structures
Analysis and simulation of multiplexed single-bus networks with and without buffering
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
A Closed-Form Solution for the Perfornance Analysis of Multiple-Bus Multiprocessor Systems
IEEE Transactions on Computers
Performance analysis of common bus multimicroprocessor systems
Journal of Systems and Software
On the product-form solution of a class of multiple-bus multiprocessor system models
Journal of Systems and Software
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In this paper we present a mathematical model to compute the bandwidth of the multiple bus interconnection network. Due to the computational complexity associated with the exact solution, the processors are removed from the queues at the end of each memory cycle to facilitate the analysis. This leads to approximate solutions which are both easier to obtain and very accurate.