Cache coherence protocols: evaluation using a multiprocessor simulation model
ACM Transactions on Computer Systems (TOCS)
ACM Transactions on Computer Systems (TOCS)
Evaluating the performance of four snooping cache coherency protocols
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
SPLASH: Stanford parallel applications for shared-memory
ACM SIGARCH Computer Architecture News
Tradeoffs in two-level on-chip caching
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Designing high bandwidth on-chip caches
Proceedings of the 24th annual international symposium on Computer architecture
The Cache-Coherence Problem in Shared-Memory Multiprocessors: Hardware Solutions
The Cache-Coherence Problem in Shared-Memory Multiprocessors: Hardware Solutions
Cache and Interconnect Architectures in Multiprocessors
Cache and Interconnect Architectures in Multiprocessors
A Trace-Driven Simulator for Performance Evaluation of Cache-Based Multiprocessor Systems
IEEE Transactions on Parallel and Distributed Systems
Utilization of Cache Area in On-Chip Multiprocessor
ISHPC '99 Proceedings of the Second International Symposium on High Performance Computing
Multiscalar Processors
The case for a single-chip multiprocessor
The case for a single-chip multiprocessor
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Advances in integrated circuit technology have led the microprocessor design to more challenging areas by providing a high budget of transistors. The one billion microprocessor is not that far from now. This leads microarchitects to look for efficient ways to make use of this feature. Chip-Multiprocessor (CMP) is one of the strong candidates in this area. Memory system for any multiprocessor is a pivotal part and can boost the performance or decrease it dramatically. The purpose of this study is to investigate the most appropriate cache memory hierarchy for CMP. We provide comparisons between several candidates and present a conclusion that can lead to better performance for CMP as well as the configurations that must be avoided.