Power-aware issue queue design for speculative instructions

Authors:
Tali Moreshet;R. Iris Bahar
Affiliations:
Brown University, Providence, RI;Brown University, Providence, RI
Venue:
Proceedings of the 40th annual Design Automation Conference
Year:
2003

Citing 11
Cited 3

Complexity-effective superscalar processors

Proceedings of the 24th annual international symposium on Computer architecture
Memory dependence prediction using store sets

Proceedings of the 25th annual international symposium on Computer architecture
Speculation techniques for improving load related instruction scheduling

ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Power and energy reduction via pipeline balancing

ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Energy-effective issue logic

ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
A large, fast instruction window for tolerating cache misses

ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Reducing power with dynamic critical path information

Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
SPEC CPU2000: Measuring CPU Performance in the New Millennium

Computer
Cache Performance of the SPEC92 Benchmark Suite

IEEE Micro
Design Challenges of Technology Scaling

IEEE Micro
Recovery Mechanism for Latency Misprediction

Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques

A low-power in-order/out-of-order issue queue

ACM Transactions on Architecture and Code Optimization (TACO)
Reducing the Energy of Speculative Instruction Schedulers

ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Co-optimization of performance and power in a superscalar processor design

EUC'06 Proceedings of the 2006 international conference on Emerging Directions in Embedded and Ubiquitous Computing

Quantified Score

Hi-index	0.00

Visualization

Abstract

Speculatively issued instructions may be particularly sensitive to increases in pipeline depth. Our results indicate that as pipeline depth increases, speculation increases the percentage of issue queue instructions that are waiting to be potentially re-issued in case of a mis-speculation. To compensate, issue queues are larger and thus more power hungry. We propose an alternative design called the Dual Issue Queue, that retains pre- and post-issue instructions in separate, smaller queues, saving 18% of issue queue power dissipation without degrading performance.