ATUM: a new technique for capturing address traces using microcode
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
The 80386DX microprocessor: hardware, software, and interfacing
The 80386DX microprocessor: hardware, software, and interfacing
Design of microprocessor-based systems
Design of microprocessor-based systems
FPGA and CPLD Architectures: A Tutorial
IEEE Design & Test
Characterization of L3 cache behavior of SPECjAppServer2002 and TPC-C
Proceedings of the 19th annual international conference on Supercomputing
Design, implementation, and verification of active cache emulator (ACE)
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
HMTT: a platform independent full-system memory trace monitoring system
SIGMETRICS '08 Proceedings of the 2008 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
HMTT: A hybrid hardware/software tracing system for bridging the DRAM access trace's semantic gap
ACM Transactions on Architecture and Code Optimization (TACO)
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Trace-driven simulation is widely used to evaluate the cache memory system. The accuracy of the trace-driven simulation depends on the accuracy and length of the trace data. To achieve an accurate and long trace, trace collection hardware is designed. The flying cache simulator is attached to the tracing system to simulate various cache systems during the execution of an application program. The tracing system designed, called the Reconfigurable Address Collector and Flying Cache Simulator (RACFCS), can generate accurate and long traces and simulate the cache system for a long execution time.