Limits of instruction-level parallelism
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Optimization of instruction fetch mechanisms for high issue rates
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Pipeline gating: speculation control for energy reduction
Proceedings of the 25th annual international symposium on Computer architecture
Dynamic IPC/clock rate optimization
Proceedings of the 25th annual international symposium on Computer architecture
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
The Alpha 21264 Microprocessor Architecture
ICCD '98 Proceedings of the International Conference on Computer Design
Compiler directed issue queue energy reduction
Transactions on High-Performance Embedded Architectures and Compilers IV
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Power dissipation is a major concern not only for portable systems, but also for high-performance systems. In the past, energy consumption and processor heating was reduced mainly by focusing efforts on mechanical or circuit design techniques. Now that we are reaching the limits of some of these past techniques, an architectural approach is fundamental to solving power related problems. In this work, we use a model of the Alpha 21264 to simulate a high-performance, multipipelined processor with two integer pipeline clusters and one floating point pipeline. We propose a hardware mechanism to dynamically monitor processor performance and reconfigure the machine on-the-fly such that available resources are more closely matched to the program's requirements. Namely, we propose to save energy in the processor by disabling one of the two integer pipelines and/or the floating point pipe at runtime for selective periods of time during the execution of a program. If these time periods are carefully selected, energy may be saved without negatively impacting overall processor performance. Our initial experiments shows on average total chip energy savings of 12% and as high as 32% for some benchmarks while performance degrades by an average of only 2.5% and at most 4.5%.