Impact of using adaptive body bias to compensate die-to-die Vt variation on within-die Vt variation
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Managing power and performance for System-on-Chip designs using Voltage Islands
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Design and reliability challenges in nanometer technologies
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2004 international symposium on Low power electronics and design
Leakage power: trends, analysis and avoidance
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Challenges in sleep transistor design and implementation in low-power designs
Proceedings of the 43rd annual Design Automation Conference
Throughput of multi-core processors under thermal constraints
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Parametric yield analysis and optimization in leakage dominated technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Characterizing chip-multiprocessor variability-tolerance
Proceedings of the 45th annual Design Automation Conference
Cost-effective power delivery to support per-core voltage domains for power-constrained processors
Proceedings of the 49th Annual Design Automation Conference
Maximizing frequency and yield of power-constrained designs using programmable power-gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Manufactured dies exhibit a large spread of maximum frequency and leakage power due to process variations, which have been increasing with technology scaling. Reducing the spread is very important for maximizing the frequency and the yield of power-constrained designs, because otherwise many dies that do not satisfy frequency or power constraints would be discarded. In this paper, we propose two optimization methods to improve the maximum operating frequency and the yield using power gates that already exist in many power-constrained designs. In the first method, we consider the designs of multiple cores, where each of them can be independently power-gated. When each core shows different frequencies due to within-die variations, the strength of a power gate in each core is adjusted to make their maximum operating frequencies even. This allows faster cores to consume less active leakage power, reducing the total power consumption well below a power constraint in a globally-clocked design. We subsequently increase global supply voltage for higher overall frequency until the power constraint is satisfied. In our experiments assuming multicore processors with 2--16 cores, the maximum operating frequency was improved by 4-23%. In the second method, we take leaky-but-fast dies (which otherwise would be discarded) and adjust the strength of the power gates such that they can operate in an acceptable power and frequency region. The problem is extended to designs employing a frequency binning strategy, where we have an additional objective of maximizing the number of dies for higher frequency bins. In our experiments with ISCAS benchmark circuits, most discarded fast-but leaky dies were recovered using the second method.