Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing
Journal of Electronic Testing: Theory and Applications
Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Improved Wafer-level Spatial Analysis for IDDQ Limit Setting
ITC '01 Proceedings of the 2001 IEEE International Test Conference
The Future of Delta IDDQ Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Practical Built-In Current Sensor for IDDQ Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
IDDX-based test methods: A survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper describes several methods for setting IDDQ pass/fail limits using cell-based process, circuit and logic simulation. We demonstrate trade-offs in accuracy and model building effort on the ISCAS85 circuits.