Model-Based IDDQ Pass/Fail Limit Setting

Authors:
T. Aruna Unni;D. M. H. Walker
Affiliations:
-;-
Venue:
IDDQ '98 Proceedings of the IEEE International Workshop on IDDQ Testing
Year:
1998

Citing 0
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Abstract

This paper describes several methods for setting IDDQ pass/fail limits using cell-based process, circuit and logic simulation. We demonstrate trade-offs in accuracy and model building effort on the ISCAS85 circuits.