Low Power Design in Deep Submicron Electronics
Low Power Design in Deep Submicron Electronics
IDDQ Test: Sensitivity Analysis of Scaling
Proceedings of the IEEE International Test Conference on Test and Design Validity
IDDQ Characterization in Submicron CMOS
Proceedings of the IEEE International Test Conference
Current Signatures: Application
Proceedings of the IEEE International Test Conference
Bridging Defects Resistance Measurements in a CMOS Process
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Model-Based IDDQ Pass/Fail Limit Setting
IDDQ '98 Proceedings of the IEEE International Workshop on IDDQ Testing
A New IDDQ Testing Scheme Employing Charge Storage BICS Circuit for Deep Submicron CMOS ULSI
IDDQ '98 Proceedings of the IEEE International Workshop on IDDQ Testing
Graphical IDDQ signatures reduce defect level and yield loss
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this work, IDDQ current for the deep sub-micron VLSI in year 2011 is estimated with a statistical approach according to the International Technology Roadmap for Semiconductors 1999 Edition considering process variations and different input vectors. The estimated results show that the standard deviation of the IDDQ current is proportional to the square root of the circuit size and the IDDQ currents of the defect-free and the defective devices, which are of the size up to 1 × 107 gates, are still differentiable under the condition of random process deviations and input vectors. Two new IDDQ testing schemes, which detect the defective current based on the two separate IDDQ distributions, are proposed. From the study, it is concluded that IDDQ testing is still applicable for the deep sub-micron VLSI for the next ten years.