Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
MD-SCAN Method for Low Power Scan Testing
ATS '02 Proceedings of the 11th Asian Test Symposium
Controlling Peak Power During Scan Testing
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
On Low-Capture-Power Test Generation for Scan Testing
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
On Reducing Peak Current and Power during Test
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
VirtualScan: A New Compressed Scan Technology for Test Cost Reduction
ITC '04 Proceedings of the International Test Conference on International Test Conference
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
XID: Don't care identification of test patterns for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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High power dissipation can occur when the response to a test vector is captured by flip-flops in scan testing, resulting in excessive IR drop, which may cause significant capture-induced yield loss in the DSM era. This paper addresses this serious problem with a novel test generation method, featuring a unique algorithm that deterministically generates test cubes not only for fault detection but also for capture power reduction. Compared with previous methods that passively conduct X-filling for unspecified bits in test cubes generated only for fault detection, the new method achieves more capture power reduction with less test set inflation. Experimental results show its effectiveness.