3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Improving linear test data compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test Data Compression Using Multi-dimensional Pattern Run-length Codes
Journal of Electronic Testing: Theory and Applications
Time-multiplexed compressed test of SOC designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Correlation-based rectangular encoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test data compression using selective encoding of scan slices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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XMAX is a novel test data compression architecture capable ofachieving almost exponential reduction in scan test data volume andtest time while allowing use of commercial Automatic Test PatternGeneration (ATPG) tools. It tolerates presence of sources ofunknown logic values (also referred to as X's) without compromisingtest quality and diagnosis capability for most practical purposes.The XMAX architecture has been implemented in several industrialdesigns.