CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
On Calculating Efficient LFSR Seeds for Built-In Self Test
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
On Reducing Peak Current and Power during Test
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
A unified submodular framework for multimodal IC Trojan detection
IH'10 Proceedings of the 12th international conference on Information hiding
Scalable hardware trojan diagnosis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FANCI: identification of stealthy malicious logic using boolean functional analysis
Proceedings of the 2013 ACM SIGSAC conference on Computer & communications security
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Testing the genuineness of a manufactured chip is an important step in an IC product life cycle. This becomes more prominent with the outsourcing of the manufacturing process, since the manufacturer may tamper the internal circuit behavior using Trojan circuits in the original design. Traditional testing methods cannot detect these stealthy Trojans because the triggering scenario, which activates it, is unknown. Recently, approaches based on side-channel analysis have shown promising results in detecting Trojans. In this paper, we propose a novel test generation technique that aims at magnifying the disparity between side-channel signal waveforms of tampered and genuine circuits to indicate the possibility of internal tampering. Experimental results indicate that our approach could magnify the likelihood of Trojans 4 to 20 times more than existing side-channel analysis based approaches.