Logic testing and design for testability
Logic testing and design for testability
Elements of the Theory of Computation
Elements of the Theory of Computation
Introduction to Automata Theory, Languages and Computability
Introduction to Automata Theory, Languages and Computability
Introduction to Algorithms
Test Calculation for Logic and Delay Faults in Digital Circuits
MTV '06 Proceedings of the Seventh International Workshop on Microprocessor Test and Verification
Polynomially Complete Fault Detection Problems
IEEE Transactions on Computers
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
A Nine-Valued Circuit Model for Test Generation
IEEE Transactions on Computers
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research and Development
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The paper is concerned with analyzing and comparing two exact algorithms from the viewpoint of computational complexity. Both are for calculating fault-detection tests for digital circuits. The first one is the so-called composite justification, and the second is the D-algorithm. The analysis will be performed on combinational logic networks at the gate level. Here single and multiple stuck-at logic faults will be considered. As a result, it is pointed out that the composite justification requires significantly less computational step than the D-algorithm and its modifications. From this fact it has been concluded that possibly no other algorithm is available in this field with fewer computational steps. If it holds, then it follows directly that the test calculation problem is of exponential-time, and so are any other NP-complete problems.