Delay test generation 2: algebra and algorithms

  • Authors:
  • Vijay S. Iyengar;Barry K. Rosen;Ilan Spillinger

  • Affiliations:
  • IBM Research Division, Yorktown Heights, NY;IBM Research Division, Yorktown Heights, NY;IBM Research Division, Yorktown Heights, NY

  • Venue:
  • ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
  • Year:
  • 1988

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Abstract

Building upon a companion paper that models the effects of delay faults of variable size on the simplified waveforms appropriate for delay testing by pairs of patterns, we introduce a new algebra for delay test generation. The algebra combines the nine natural logic values (00, 01, 0X, 10, 11, 1X, X0, X1, XX ) with special attributes that record both heuristic choices and whatever information about waveforms is deducible algebraically (i.e., without numerical computations using actual gate delays). A new test generator uses this algebra in an efficiently organized backtrack search. If a delay fault has robust tests, then they will be found relatively early in the search. If a delay fault does not have any robust tests, then the search will still find tests with relatively few dependencies on delays outside the propagation paths. The search is therefore biased toward robust tests without being restricted to them. Similarly, the search is biased toward single path propagation without being restricted to it. Ours is the first delay test generator to be logically complete. Given any testable fault, it will eventually find a test. Like test generators for stuck-at faults, however, it will be incomplete in practice because of a limit on the amount of backtracking. A new technique for accelerated backtracking enhances the likelihood of finding a test before the limit is reached. This technique divides test generation into phases, and the phase of each stacked decision is remembered. Exploration of a subtree of the decision tree may be truncated by backtracking all the way to a phase boundary. Finally, the test generator is linked to a new delay fault simulator. Previous event-driven simulators have considered different types of events. One type of event is a change in faultless values from one test to another test; another type of event is a difference between faulty and faultless values. Our simulator is driven by both types of events. Each generated test is simulated to determine the quality of detection (as defined in the companion paper).