Polynomially Complete Fault Detection Problems
IEEE Transactions on Computers
Fault Testing and Diagnosis in Combinational Digital Circuits
IEEE Transactions on Computers
Analyzing Errors with the Boolean Difference
IEEE Transactions on Computers
Uncertainty, Energy, and Multiple-Valued Logics
IEEE Transactions on Computers
Test Sets for Combinational Logic The Edge-Tracing Approach
IEEE Transactions on Computers
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
B-algorithm: a behavioral test generation algorithm
ITC'94 Proceedings of the 1994 international conference on Test
Delay test generation 2: algebra and algorithms
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Automatic test pattern generation with BOA
PPSN'06 Proceedings of the 9th international conference on Parallel Problem Solving from Nature
| Hi-index | 14.99 |
An algorithm for generating test patterns for combinational circuits has been developed and programmed. The algorithm is definitive and finds a test for all faults including those that require multiple paths to be sensitized, by sensitizing a single path at a time and trying at most each single path. This is achieved by using a new calculus based on nine values (0,1,D,D炉,0/D,0/D炉, 1/D,1/D炉,U). One path is deliberately sensitized while the alternative paths are assigned values which permit the option of desensitizing or sensitizing them as the sensitized path is developed. Experimental results are presented for a variety of cases.