9-V Algorithm for Test Pattern Generation of Combinational Digital Circuits
IEEE Transactions on Computers
Fault-Tolerant Computing: An Introduction and a Viewpoint
IEEE Transactions on Computers
Use of SPOOF's in the Analysis of Faulty Logic Networks
IEEE Transactions on Computers
On the Properties of Sensitized Paths
IEEE Transactions on Computers
Fault Testing and Diagnosis in Combinational Digital Circuits
IEEE Transactions on Computers
Partitioning of Separating Edges: A New Approach to Combinational Logic Design
IEEE Transactions on Computers
On the Design of Minimum Length Fault Tests for Combinational Circuits
IEEE Transactions on Computers
Fault-Tolerant Computing: An Introduction and an Overview
IEEE Transactions on Computers
An Efficient Algorithm for Generating Complete Test Sets for Combinational Logic Circuits
IEEE Transactions on Computers
Designing Sets of Fault-Detection Tests ror Combinational Logic Circuits
IEEE Transactions on Computers
On the necessity to examine D-chains in diagnostic test generation-an example
IBM Journal of Research and Development
General Criterion for Essential Nonfault Locatability of Logical Functions
IEEE Transactions on Computers
| Hi-index | 14.98 |
A method for fault analysis of multilevel combinational logic circuits with single stuck-at-faults is described. It determines the sensitizing input combinations (separating edges) from the output function and then traces their paths from the output toward the inputs. The handling of multiple path sensitization in this approach is much simpler than in other path-tracing techniques. Subscripting of variables is not needed and dead-ending (as encountered in the D-algorithm) cannot occur.