Uncertainty, Energy, and Multiple-Valued Logics
IEEE Transactions on Computers
Microprogrammed operations for a three-value logic simulator
MICRO 7 Conference record of the 7th annual workshop on Microprogramming
A Switch-Level Model and Simulator for MOS Digital Systems
IEEE Transactions on Computers
Functional Level Primitives in Test Generation
IEEE Transactions on Computers
Dynamic Testing of Redundant Logic Networks
IEEE Transactions on Computers
On the Three-Valued Simulation of Digital Systems
IEEE Transactions on Computers
A Note on a Modified Ternary Simulator Capable of Initializing All Fault Machine Memory Elements
IEEE Transactions on Computers
Test generation for MOS circuits
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Ternary simulation: refinement of binary functions or abstraction of real-time behaviour?
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
Constructive Boolean circuits and the exactness of timed ternary simulation
Formal Methods in System Design
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In this note we discuss a few attributes and pitfalls of three-valued (0, 1, u) digital logic simulation. The areas covered include hazard and race detection, fault detection, verifying the reset logic of a machine, and the problems encountered with self-timing circuits and in employing a complement for u.