Introduction to algorithms
Symbolic prime generation for multiple-valued functions
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Implicit and incremental computation of primes and essential primes of Boolean functions
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A framework for satisfying input and output encoding constraints
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Zero-suppressed BDDs for set manipulation in combinatorial problems
DAC '93 Proceedings of the 30th international Design Automation Conference
Espresso-signature: a new exact minimizer for logic functions
DAC '93 Proceedings of the 30th international Design Automation Conference
On the hardness of approximating minimization problems
STOC '93 Proceedings of the twenty-fifth annual ACM symposium on Theory of computing
New ideas for solving covering problems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A framework for the analysis and design of algorithms for a class of VLSI-CAD optimization problems
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Exact Dichotomy-based Constrained Encodi
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Optimum logic encoding and layout wiring for vlsi design: a graph-theoretic approach
Optimum logic encoding and layout wiring for vlsi design: a graph-theoretic approach
Exact two-level minimization of hazard-free logic with multiple-input changes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LFSR-Based Deterministic TPG for Two-Pattern Testing
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
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This article introduces a mathematical framework called cluster-cover. We show that this framework captures the combinatorial structure of a class of VLSI design optimization problems, including two-level logic minimization, constrained encoding, multilayer topological planar routing, application timing assignment for delay-fault testing, and minimization of monitoring logic for BIST enchancement. These apparently unrelated problems can all be cast into two metaproblems in our framework: finding a maximum cluster and finding a minimum cover. We describe paradigms for developing algorithms for these problems. First, a simple heuristic called greedy peeling is presented and characterized. We derive sufficient conditions that guarantee optimum solutions by greedy peeling. We generalize the performance analysis of a multilayer topological planar routing heuristic to greedy peeling for the general cluster-cover problems. We propose a performance bound of greedy set covering that can be computed efficiently for a given problem instance; this bound is much tighter than the previously known bounds. Second, prime covering—orignally developed for logic minimization—is generalized to finding exact solutions for cluster-cover problems. Previously, only the connection between logic minimizaton and constrained encoding was known.